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low voltage, lvcmos/lvpecl-to lvpecl/ecl clock generator ics873991-147 idt ? / ics ? lvpecl/ecl clock generator 1 ics873991ay-147 rev. a august 10, 2007 preliminary g eneral d escription the ics873991-147 is a low voltage, low skew, 3.3v lvpecl or ecl clock generator and a member of the hiperclocks? family of high performance clock solutions from idt. the ics873991-147 has two selectable clock inputs. the pclk, npclk pair can accept an lvpecl input and the ref_clk pin can accept a lvcmos or lvttl input. this device has a fully integrated pll along with frequency configurable outputs. an external feedback input and output regenerates clocks with ?zero de- lay?. the four independent banks of outputs each have their own output dividers, which allow the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. the output frequency range is 25mhz to 500mhz and the input frequency range is 6.25mhz to 125mhz. the pll_sel input can be used to bypass the pll for test and system debug purposes. in bypass mode, the input clock is routed around the pll and into the internal output dividers. the ics873991-147 also has a sync output which can be used for system synchronization purposes. it monitors bank a and bank c outputs for coincident rising edges and signals a pulse per the timing diagrams in this data sheet. this feature is used primarily in applications where bank a and bank c are running at different frequencies, and is particularly useful when they are running at non-integer multiples of each other. example applications: 1. line card multiplier: multiply 19.44mhz from a back-plane to 77.76mhz on the line card asic and serdes. 2. zero delay buffer: fan out up to thirteen 100mhz copies from a reference clock to multiple processing units on an embedded system. hiperclocks? ic s f eatures ? fourteen differential 3.3v lvpecl/ecl outputs ? selectable differential lvpecl or ref_clk inputs ? pclk, npclk can accept the following input levels: lvpecl, cml, sstl ? ref_clk accepts the following input levels: lvcmos, lvttl ? input clock frequency range: 6.25mhz to 125mhz ? maximum output frequency: 500mhz ? vco range: 200mhz to 1ghz ? output skew: 70ps (typical) ? cycle-to-cyle jitter: 35ps (typical) ? lvpecl mode operating voltage supply range: v cc = 3.135v to 3.465v, v ee = 0v ? ecl mode operating voltage supply range: v cc = 0v, v ee = -3.465v to -3.135v ? 0c to 70c ambient operating temperature ? available in lead-free (rohs 6) package ? industrial temperature available upon request p in a ssignment v ee mr pll_en ref_sel fsel_fb2 fsel_fb1 fsel_fb0 ref_clk pclk npclk v cc ext_fb next_fb nqb3 qb3 v cco nqa0 qa0 nqa1 qa1 nqa2 qa2 nqa3 qa3 sync_sel vco_sel 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 24 23 22 21 20 19 18 17 16 15 14 39 38 37 36 35 34 33 32 31 30 29 28 27 qc1 nqc1 qc0 nqc0 v cco qd1 nqd1 qd0 nqd0 v cco qfb nqfb v cca fsel0 qb2 nqb2 fsel1 qb1 nqb1 fsel2 qb0 nqb0 v cco qc2 nqc2 fsel3 ics873991-147 52-lead lqfp 10mm x 10mm x 1.4mm package body y package top view the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? lvpecl/ecl clock generator 2 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary phase detector lpf vco frequency generator sync vco_sel pll_en ref_sel ref_clk npclk pclk ext_fb next_fb mr fsel_0:3 fsel_fb0:2 sync_sel qa0 nqa0 qa1 nqa1 qa2 nqa2 qa3 nqa3 qb0 nqb0 qb1 nqb1 qb2 nqb2 qb3 nqb3 qc0 nqc0 qc1 nqc1 qc2 nqc2 qd0 nqd0 qd1 nqd1 qfb nqfb b lock d iagram pulldown pulldown pulldown pulldown pulldown pulldown pulldown pulldown
idt ? / ics ? lvpecl/ecl clock generator 3 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 1v e e r e w o p. n i p y l p p u s e v i t a g e n 2r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a s t u p t u o d e t r e v n i e h t d n a w o l o g o t ) x q ( s t u p t u o e u r t e h t g n i s u a c t e s e r s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t ) x q n ( . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a 3n e _ l l pt u p n in w o d l l u p , h g i h c i g o l n e h w . d e l b a n e s i l l p , w o l c i g o l n e h w . n i p e l b a n e l l p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e d o m s s a p y b n i s i l l p 4l e s _ f e rt u p n in w o d l l u p e c n e r e f e r l l p e h t s a s t u p n i e c n e r e f e r t n e r e f f i d e h t n e e w t e b s t c e l e s , h g i h c i g o l n e h w . k l c p n / k l c p s t c e l e s , w o l c i g o l n e h w . e c r u o s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k l c _ f e r s t c e l e s 5 6 7 2 b f _ l e s f 1 b f _ l e s f 0 b f _ l e s f t u p n in w o d l l u p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s n i p t c e l e s y c n e u q e r f k c a b d e e f 8k l c _ f e rt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c e c n e r e f e r 9k l c pt u p n in w o d l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i - n o n 0 1k l c p nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / 1 1v c c r e w o p. n i p y l p p u s e r o c 2 1b f _ t x et u p n in w o d l l u p. t u p n i k c a b d e e f l a n r e t x e g n i t r e v n i - n o n 3 1b f _ t x e nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c a b d e e f l a n r e t x e g n i t r e v n i c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / 4 1v a c c r e w o p. n i p y l p p u s g o l a n a 5 1 6 1 b f q n b f q t u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o k c a b d e e f l a i t n e r e f f i d 2 4 , 0 3 , 2 2 , 7 1v o c c r e w o p. s n i p y l p p u s t u p t u o 9 1 , 8 10 d q , 0 d q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 1 2 , 0 21 d q , 1 d q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 4 2 , 3 20 c q , 0 c q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 6 2 , 5 21 c q , 1 c q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 7 2 3 3 6 3 9 3 3 l e s f 2 l e s f 1 l e s f 0 l e s f t u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s n i p t c e l e s y c n e u q e r f 9 2 , 8 22 c q , 2 c q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 2 3 , 1 30 b q , 0 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 3 , 4 31 b q , 1 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8 3 , 7 32 b q , 2 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 1 4 , 0 43 b q , 3 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 4 4 , 3 40 a q , 0 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 6 4 , 5 41 a q , 1 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8 4 , 7 42 a q , 2 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 5 , 9 43 a q , 3 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 1 5l e s _ c n y st u p n in w o d l l u p e h t s w o l l o f t u p u t o c n y s e h t , w o l n e h w . n i p t c e l e s t u p t u o c n y s t u p t u o c q s w o l l o f t u p t u o d q , h g i h n e h w . ) 5 e g a p ( m a r g a i d g n i m i t . . s l e v e l e c a f r e t n i l t t v l / s o m c v l 2 5l e s _ o c vt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . e g n a r o c v s t c e l e s : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
idt ? / ics ? lvpecl/ecl clock generator 4 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary t able 3b. f eedback c ontrol f unction t able s t u p n is t u p t u o 2 b f _ l e s f1 b f _ l e s f0 b f _ l e s fb f q 0002 00 14 0106 0118 10 0 8 10 1 6 1 110 4 2 111 2 3 t able 3a. s elect p in f unction t able t able 3c. i nput c ontrol f unction t able n i p t u p n i l o r t n o c0 c i g o l1 c i g o l n e _ l l pl l p s e l b a n el l p s e s s a p y b l e s _ o c vo c v f2 / o c v f l e s _ f e rk l c p n / k l c p s t c e l e sk l c _ f e r s t c e l e s r m- - -s t u p t u o s t e s e r l e s _ c n y ss t u p t u o s t c e l e ss t u p t u o c q h c t a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k t able 2. p in c haracteristics s t u p n is t u p t u o 3 l e s f2 l e s f1 l e s f0 l e s fx a qx b qx c q 00 0 02 2 2 00 0 12 2 4 00 102 4 4 00 1 12 2 6 01002 6 6 010 12 4 6 01102 4 8 01112 6 8 10 0 02 2 8 10 0 12 8 8 10 1 04 4 6 10 1 14 6 6 110 04 6 8 110 16 6 8 11 106 8 8 11 1 18 8 8
idt ? / ics ? lvpecl/ecl clock generator 5 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary 1:1 mode 2:1 mode 3:1 mode 3:2 mode 4:3 mode f igure 1. t iming d iagrams qa qc sync (qd) qa qc sync (qd) qa qc sync (qd) qa qc sync (qd) qa qc sync (qd)
idt ? / ics ? lvpecl/ecl clock generator 6 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary t able 4a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o5 3 1 . 33 . 35 6 4 . 3v i c c t n e r r u c y l p p u s r e w o p 0 5 1a m i a c c t n e r r u c y l p p u s g o l a n a 5 1a m i o c c t n e r r u c y l p p u s t u p t u o 5 9a m a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja 63.7c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these rat- ings are stress specifications only. functional operation of prod- uct at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. ex- posure to absolute maxi-mum rating conditions for extended pe- riods may affect product reliability. t able 4c. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c t able 4b. lvcmos/lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i , l e s _ o c v , n e _ l l p , l e s _ c n y s , l e s _ f e r , 2 b f _ l e s f : 0 b f _ l e s f r m , 3 l e s f : 0 l e s f 2v c c 3 . 0 +v k l c _ f e r2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i , l e s _ o c v , n e _ l l p , l e s _ c n y s , l e s _ f e r , 2 b f _ l e s f : 0 b f _ l e s f r m , 3 l e s f : 0 l e s f 3 . 0 -8 . 0v k l c _ f e r3 . 0 -3 . 1v i h i t n e r r u c h g i h t u p n iv c c v = n i v 5 6 4 . 3 =0 5 1a i l i t u p n it n e r r u c w o lv n i v , v 0 = c c v 5 6 4 . 3 =5 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c pv c c v = n i v 5 6 4 . 3 =0 5 1a k l c p nv c c v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i k l c pv c c v , v 5 6 4 . 3 = n i v 0 =5 -a k l c p nv c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 3 . 01v v r m c 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 1 +v c c v v h o 2 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 2 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 01v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . 0 5 h t i w d e t a n i m r e t s t u p t u o : 2 e t o n v o t o c c . . v 2 -
idt ? / ics ? lvpecl/ecl clock generator 7 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary t able 6. ac c haracteristics , v cc = v cca = v cco = 3.3v 5%, t a = 0c to 70c t able 5. pll i nput r eference c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c note: these parameters are guaranteed by design, but are not tested in production. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o c q , b q , a q 0 0 5z h m d q1 = l e s _ c n y s0 0 4z h m 1 e t o n ; d q0 = l e s _ c n y s0 0 2z h m ) ? ( t ; t e s f f o e s a h p c i t a t s 3 , 2 e t o n k l c p n , k l c p0 7 1s p t ) o ( k s5 , 4 e t o n ; w e k s t u p t u o 0 7s p t ) w ( k s6 , 5 e t o n ; w e k s y c n e u q e r f e l p i t l u m d b ts p t ) c c ( t i j5 e t o n ; r e t t i j e l c y c - o t - e l c y c 5 3s p f o c v 7 e t o n ; e g n a r k c o l o c v l l p 0 = l e s _ l l p4 . 00 . 1z h g 1 = l e s _ l l p0 0 20 8 4z h m t k c o l e m i t k c o l l l p 0 1s m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 25 . 0s n c d oe l c y c y t u d t u p t u o 0 5% t a d e r u s a e m s r e t e m a r a p l l af x a m . e s i w r e h t o d e t o n s s e l n u : 1 e t o n . y c n e u q e r f o c v m u m i x a m z h m 0 0 8 o t d e e t n a r a u g n o i t a r e p o ) 0 = l e s _ c n y s n e h w d q ( t u p t u o c n y s l a n g i s t u p n i k c a b d e e f e g a r e v a e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 2 e t o n . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . 8 n i k c a b d e e f h t i w z h m 0 5 f o y c n e u q e r f t u p n i n a r o f d e i f i c e p s s i t e s f f o e s a h p c i t a t s : 3 e t o n : 4 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m : 5 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t s e i c n e u q e r f t n e r e f f i d t a g n i t a r e p o n o i t c e r i d e m a s e h t n i g n i h c t i w s s t u p t u o f o s k n a b s s o r c a w e k s s a d e n i f e d : 6 e t o n v t a d e r u s a e m . s n o i t i d n o c d a o l l a u q e d n a s e g a t l o v y l p p u s e m a s e h t h t i w o c c . 2 / . 6 e m o s d n a 4 , 2 f o s n o i t a r u g i f n o c k c a b d e e f h t i w e l b a t s n u e b l l i w l l p e h t , 0 = l e s _ o c v n e h w : 7 e t o n . 2 f o n o i t a r u g i f n o c k c a b d e e f a h t i w e l b a t s n u e b l l i w l l p e h t , 1 = l e s _ o c v n e h w l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u t r t / r e m i t l l a f / e s i r t u p n ik l c _ f e r3s n f f e r y c n e u q e r f e c n e r e f e r 0 = l e s _ o c v 6 k c a b d e e f6 6 . 6 67 6 . 6 6 1z h m 8 k c a b d e e f0 55 2 1z h m 6 1 k c a b d e e f5 25 . 2 6z h m 4 2 k c a b d e e f6 6 . 6 17 6 . 1 4z h m 2 3 k c a b d e e f5 . 2 15 2 . 1 3z h m y c n e u q e r f e c n e r e f e r 1 = l e s _ o c v 4 k c a b d e e f0 50 0 1z h m 6 k c a b d e e f3 3 . 3 36 6 . 6 6z h m 8 k c a b d e e f5 20 5z h m 6 1 k c a b d e e f5 . 2 15 2z h m 4 2 k c a b d e e f3 3 . 86 6 . 6 1z h m 2 3 k c a b d e e f5 2 . 65 . 2 1z h m f c d f e r e l c y c y t u d t u p n i e c n e r e f e r 5 25 7%
idt ? / ics ? lvpecl/ecl clock generator 8 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary p arameter m easurement i nformation o utput r ise /f all t ime o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v v ee t sk(o) nqx qx nqy qy qfb, qax:qdx nqfb, nqax:nqdx -1.3v -0.165v v cc , v cca , v cco s tatic p hase o ffset o utput s kew pclk npclk clock outputs 20% 80% 80% 20% t r t f v sw i n g ? ? t (?) v oh v ol v oh v ol m ultiple f requency s kew d ifferential i nput l evels ? ? ? ? t cycle n t cycle n+1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t pw t period t pw t period odc = x 100% qfb, qax:qdx nqfb, nqax:nqdx c ycle - to -c ycle j itter v cmr cross points v pp v cc v ee pclk npclk o utput d uty c ycle /p ulse w idth /p eriod tsk( ) nqxx qxx nqyy qyy nqfb, nqax:nqdx qfb, qax:qdx
idt ? / ics ? lvpecl/ecl clock generator 9 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary figure 3 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 3. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics873991-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply iso- lation is required. figure 2 illustrates how a 10 resistor along with a 10 f and a 0.01 f bypass capacitor should be con- nected to each v cca pin. f igure 2. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc p ower s upply f iltering t echniques a pplications i nformation vcc r2 1k v_ref c1 0.1u r1 1k single ended clock input pclk npclk
idt ? / ics ? lvpecl/ecl clock generator 10 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary lvpecl c lock i nput i nterface the pclk/npclk accepts lv pecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4e show interface examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. f igure 4c. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 4e. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvds d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm c2 r2 1k r5 100 zo = 50 ohm 3.3v 3.3v c1 r3 1k lvds r4 1k hiperclocks pclk npclk r1 1k zo = 50 ohm 3.3v pclk/npclk 3.3v r5 100 - 200 3.3v 3.3v hiperclocks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl f igure 4d. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple 3.3v 3.3v cml built-in pullup r1 100 pclk npclk hiperclocks pclk/npclk zo = 50 ohm zo = 50 ohm f igure 4a. h i p er c lock s pclk/npclk i nput d riven by an o pen c ollector cml d river f igure 4b. h i p er c lock s pclk/npclk i nput d riven by a b uilt -i n p ullup cml d river
idt ? / ics ? lvpecl/ecl clock generator 11 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, termi- nating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to f igure 5b. lvpecl o utput t ermination f igure 5a. lvpecl o utput t ermination drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs i nputs : pclk/npclk i nputs for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k resistor can be tied from pclk to ground. lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
idt ? / ics ? lvpecl/ecl clock generator 12 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary t able 7. t hermal r esistance ja for 52-p in lqfp f orced c onvection p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics873991-147. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics873991-147 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 150ma = 519.75mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 14 * 30mw = 420mw total power _max (3.465v, with all outputs switching) = 519.75mw + 420mw = 939.75mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 55.5c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.940w * 55.5c/w = 122.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 63.7c/w 55.5c/w 52.4c/w
idt ? / ics ? lvpecl/ecl clock generator 13 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
idt ? / ics ? lvpecl/ecl clock generator 14 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary r eliability i nformation t ransistor c ount the transistor count for ics873991-147 is: 5969 t able 8. ja vs . a ir f low t able for 52 l ead lqfp ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 63.7c/w 55.5c/w 52.4c/w
idt ? / ics ? lvpecl/ecl clock generator 15 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary p ackage o utline - y s uffix for 52 l ead lqfp t able 9. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s c c b m u m i n i ml a n i m o nm u m i x a m n 2 5 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 2 2 . 02 3 . 08 3 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 2 1 1 d c i s a b 0 0 . 0 1 2 d . f e r 0 8 . 7 e c i s a b 0 0 . 2 1 1 e c i s a b 0 0 . 0 1 2 e . f e r 0 8 . 7 e c i s a b 5 6 . 0 l 5 4 . 0- -5 7 . 0 0 - - 7 c c c - -- -0 1 . 0
idt ? / ics ? lvpecl/ecl clock generator 16 ics873991ay-147 rev. a august 10, 2007 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments. t able 10. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t f l 7 4 1 - y a 1 9 9 3 7 8l 7 4 1 a 1 9 9 3 7 8 s c ip f q l " e e r f - d a e l " d a e l 2 5y a r tc 0 7 o t c 0 t f l 7 4 1 - y a 1 9 9 3 7 8l 7 4 1 a 1 9 9 3 7 8 s c ip f q l " e e r f - d a e l " d a e l 2 5l e e r & e p a t 0 0 5c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ics873991-147 low voltage, lvcmos/lvpecl-to-lvpecl/ecl clock generator preliminary ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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